ASIC Verification Engineer
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Description de l’offre d’emploi
Senior engineer 5+ years experience in ASIC Verification. Experience in the following is essential:VHDL or Verilog, Building Testbenchs for ASIC
Experience in the following are highly desirable: Systemverilog, Specman, ideally with UVM Systemverilog and Formal Property Checking.
Attractive package on offer.