Job offer description

Senior engineer 5+ years experience in ASIC Verification.  Experience in the following is essential:VHDL or Verilog, Building Testbenchs for ASIC

Experience in the following are highly desirable: Systemverilog, Specman, ideally with UVM Systemverilog and Formal Property Checking. 

Attractive package on offer.

Job details
Sector:
Professional, scientific and technical activities
Occupation field:
Engineering professionals (excluding electrotechnology)
Work experience:
Work experience is required
Duration of work experience:
More than 5 years
Salary range:
Not provided
Date of expiry:
Link for more information:
ASIC Verification

About company

Chipright is a leading provider of internationally traded design services in the fields of micro-electronic design and development. We support customers design and verification activities with our network of consultants. Find out more