26890 - ASIC Digital Design Engineer
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Synopsys' leading DesignWare IP portfolio is developed by an IP Design Team within Synopsys’ Solutions Group. Part of the Team is located in Lisbon and is staffed with analog and digital IC design engineers, application engineers and test engineers among others. The company's extensive IP portfolio enables next-generation SoC designers to integrate silicon-proven functionality previously available only to large integrated device manufacturers. The IP is licensed to leading semiconductor companies across all major markets, offering high-precision, single-function blocks to complete interface sub-systems.
ASIC Digital Design Engineer
Synopsys, a world leader in the Semiconductor IP industry, is seeking a Digital Front-End Verification Engineer whose mandate is to:
- Work in a Digital and Verification Development team contributing to the development and validation of complex digital mix signals for high-speed interface IP.
- Engage in verification activities under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
- Exposure to mixed signal validations flow. Co-sim.
- Build productive working relationships, mostly within the team.
- Participate in applicable product/project reviews.
- Prepare and present reports outlining the outcome of technical projects.
Key Qualifications
- University degree in electronics engineering or computer science
- Deep Knowledge of IC design flows
- Analog design knowledge
- Analog tools and spice simulators understanding
- Willingness to learn new things
- Good team-player
- Organizational skills are essential
- Good problem-solving skills
- Good English communication skills
Preferred Experience
- 2+ years of relevant experience is highly preferred
- Experience in producing high-quality technical documentation is desirable
- Experience in Verilog/VHDL
- Proficiency in at least on programming language such as Python, C, C++ and MatLab
- Experience in System Verilog or VMM or OVM or UVM
- Exposure to Unix, Perl and TCL scripting
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
