Verification Engineer

Job Description:

- Generates the test bench modules and scripts for verification

- Creates test case definitions based on design specifications

- Develops test cases according to test case definition

- Collects & tracks coverage data

- Is responsible for test script development and maintenance

- Simulates the needed functionality on Top-Level and Block-Level

- Ensures effective testing and high quality product delivery

- Report and analyze product’s defects

- Prepares and reviews System-on-Chip test documentation

Skills:

- good understanding of advanced verification methodologies (UVM/OVM & SystemVerilog)

-  good understanding of low level SW (ASM & C) development

- good understanding of ARM based platforms

-  good VHDL/Verilog/System Verilog knowhow and coding and modeling experience

-  good knowledge of SoC (ASIC/FPGA) verification tools, e.g. simulator, Matlab

-  good understanding of industry standard VIPs (e.g. Synopsys VIPs & Mentor VIPs)

-  good understanding of code coverage tracking tools/methodologies as well as defining functional coverage for design

- Good understanding of the SoC (ASIC/FPGA) design and verification flow and process.

- Solid background in Protocol testing (SW feature level verification), functional testing (overall feature in different system configurations) and performance testing (environmental, EMC, safety) related persons needed.

- Background in Cellular networks and 2G, 3G and LTE technology

Tools:

- VCS, QuestaSim, Verdi, Matlab, VIPs from Synopsys & Mentor