R&D Engineer OPC and Design Technology Co-Optimization

The Advanced Patterning Center (APC) is a joint initiative launched by imec and ASML to address the upcoming scaling challenges associated with the chip industry’s move towards single digit nanometer dimensions. The center is located at the imec campus in Leuven (near Brussels) and is expected to grow continuously over the next couple of years. The APC is associated with the imec Supplier Hub, an initiative involving many leading edge semiconductor equipment suppliers, aimed at creating a collaborative environment to investigate the practical interactions between all the different steps in the chip patterning process. The APC and Supplier Hub will use actual devices to analyze and optimize process steps as well as materials and device architecture choices, while applying integrated metrology. For the APC we are looking for an R&D Engineer OPC and Design Technology Co-Optimization (m/f). Job description You will develop and qualify OPC technology on imec 7nm node and beyond. Therefore you possess strong lithography/OPC knowledge in FEOL and/or BEOL; and good understanding of high performance CMOS patterning/design integration. You are experienced in lithography/OPC process development and must be capable of collaborating with process integration development teams, as well as designers. Previous technology development experience is a plus. Specific responsibilities will include: - Development of OPC technology for imec 7nm node and beyond. - Definition/assessment of Design Rules for imec 7nm node and beyond. - Collaboration with EDA partners on innovative computational lithography solutions.