Job Description:
- Perform algorithm development and optimization for HW implementation
- Implement of signal processing features (digital RF) at RTL level (VHDL)
- Perform RTL quality checks and Clock Domain Crossing checks
- Verification and simulation of needed functionality on block level
- Prepares and reviews System-on-Chip development documentations and application documents
- Cooperate with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality
Skills:
- Excellent VHDL knowhow and many years of RTL coding and modeling experience
- Matlab and other system modeling tools
- Good understanding of advanced verification methodologies, e.g UVM/OVM & SystemVerilog
- Complete understanding of the SoC (ASIC/FPGA) design flow and process.
- Knowledge of SoC (ASIC/FPGA) design and verification tools.
- Knowledge of IP-XACT-1685 schema
- Solid background in Cellular networks and 2G and 3G technology
Tools:
Magillem, Atrenta Spgyglass, VCS, QuestaSim, design Compiler, Matlab & Simulink.